Design of cost-efficient interconnect processing units : Spidergon STNoC /

This book presents streamlined design solutions specifically for NoC. To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level...

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Bibliographic Details
Corporate Author:	Taylor & Francis
Other Authors:	Coppola, Marcello
Format:	eBook
Language:	English
Published:	Boca Raton : CRC Press, ©2009.
Series:	System-on-chip design and technologies.
Subjects:	ST Microelectronics. ST Microelectronics Networks on a chip. Microprocessors. Réseaux sur puce. COMPUTERS > Hardware > Mainframes & Minicomputers. Microprocessors Networks on a chip Mikroprocessorer. Electronic books.
Online Access:	Connect to the full text of this electronic book

Table of Contents:

1. Towards multicores : technology and software complexity
2. On-chip bus vs. network-on-chip
3. NoC topology
4. The Spidergon STNoC
5. SoC and NoC design methodology and tools
6. Conclusions and future work
References
Index.