Design of cost-efficient interconnect processing units : Spidergon STNoC /
This book presents streamlined design solutions specifically for NoC. To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level...
| Corporate Author: | |
|---|---|
| Other Authors: | |
| Format: | eBook |
| Language: | English |
| Published: |
Boca Raton :
CRC Press,
©2009.
|
| Series: | System-on-chip design and technologies.
|
| Subjects: | |
| Online Access: | Connect to the full text of this electronic book |
| Summary: | This book presents streamlined design solutions specifically for NoC. To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques. A Balanced Analysis of NoC Architecture - As the first detailed description of the commercial Spidergon STNoC architecture, "Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC" examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (SoC) applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks. From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns. It is an arsenal of practical learning tools at your disposal |
|---|---|
| Physical Description: | 1 online resource (xxi, 265 pages) : illustrations |
| Bibliography: | Includes bibliographical references (pages 235-261) and index. |
| ISBN: | 9781420044720 1420044729 1420044710 9781420044713 1281863149 9781281863140 9781315219936 131521993X 9781351827133 1351827138 |