ASIC and FPGA Verification /

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate v...

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Bibliographic Details

Main Author:	Munden, Richard (Author)
Corporate Author:	Safari, an O'Reilly Media Company
Format:	eBook
Language:	English
Published:	Morgan Kaufmann, 2004.
Edition:	1st edition.
Subjects:	Electronic books.
Online Access:	Connect to this electronic resource