Verification Techniques for System-Level Design /
This book will explain how to verify SoC (Systems on Chip) logic designs using "formal” and "semiformal” verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the...
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| Format: | eBook |
| Language: | English |
| Published: |
Morgan Kaufmann,
2010.
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| Edition: | 1st edition. |
| Subjects: | |
| Online Access: | Connect to this electronic resource |
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