Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog /

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrat...

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Bibliographic Details

Main Author:	Taraate, Vaibbhav (Author)
Corporate Author:	SpringerLink (Online service)
Format:	eBook
Language:	English
Published:	Singapore : Springer Singapore : Imprint: Springer, 2019.
Edition:	1st ed. 2019.
Subjects:	Electronic circuits. Microprogramming. Logic design. Circuits and Systems. Control Structures and Microprogramming. Logic Design.
Online Access:	Connect to the full text of this electronic book