Digital Timing Macromodeling for VLSI Design Verification /
Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level s...
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| Format: | eBook |
| Language: | English |
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Boston, MA :
Springer US,
1995.
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| Series: | Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing ;
319. |
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| Online Access: | Connect to the full text of this electronic book |
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