Formal Semantics and Proof Techniques for Optimizing VHDL Models /
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to r...
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| Format: | eBook |
| Language: | English |
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Boston, MA :
Springer US,
1999.
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| Online Access: | Connect to the full text of this electronic book |
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