Formal Semantics and Proof Techniques for Optimizing VHDL Models /

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to r...

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Bibliographic Details

Main Author:	Umamageswaran, Kothanda
Corporate Author:	SpringerLink (Online service)
Other Authors:	Pandey, Sheetanshu L., Wilsey, Philip A.
Format:	eBook
Language:	English
Published:	Boston, MA : Springer US, 1999.
Subjects:	Engineering. Computer input-output equipment. Computer-aided design. Computer engineering. Systems engineering. Electronic books. Computers.
Online Access:	Connect to the full text of this electronic book