High Level Synthesis of ASICs under Timing and Synchronization Constraints /

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in th...

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Bibliographic Details

Main Author:	Ku, David C.
Corporate Author:	SpringerLink (Online service)
Other Authors:	Micheli, Giovanni
Format:	eBook
Language:	English
Published:	Boston, MA : Springer US, 1992.
Series:	Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing ; 177.
Subjects:	Engineering. Computer-aided design. Computer engineering. Systems engineering. Electronic books.
Online Access:	Connect to the full text of this electronic book