Formal Semantics for VHDL /
It is recognized that formal design and verification methods are an important requirement for the attainment of high quality system designs. The field has evolved enormously during the last few years, resulting in the fact that formal design and verification methods are nowadays supported by several...
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| Format: | eBook |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
1995.
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| Series: | Kluwer international series in engineering and computer science. VLSI, computer architecture, and digital signal processing ;
307. |
| Subjects: | |
| Online Access: | Connect to the full text of this electronic book |
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