Design methodologies for built-in testing of integrated RF transceivers with the on-chip loopback technique /
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[College Station, Tex.] :
[Texas A&M University],
[2010]
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| Online Access: | Link to OAK Trust copy |
| Abstract: | Advances toward increased integration and complexity of radio frequency (RF) and mixed-signal integrated circuits reduce the effectiveness of contemporary test methodologies and result in a rising cost of testing. The focus in this research is on the circuit-level implementation of alternative test strategies for integrated wireless transceivers with the aim to lower test cost by eliminating the need for expensive RF equipment during production testing. The first circuit proposed in this thesis closes the signal path between the transmitter and receiver sections of integrated transceivers in test mode for bit error rate analysis at low frequencies. Furthermore, the output power of this on-chip loopback block was made variable with the goal to allow gain and 1-dB compression point determination for the RF front-end circuits with on-chip power detectors. The loopback block is intended for transceivers operating in the 1.9-2.4GHz range and it can compensate for transmitter receiver offset frequency differences from 40MHz to 200MHz. The measured attenuation range of the 0.052mm2 loopback circuit in 0.13[micron] CMOS technology was 26-41dB with continuous control, but post-layout simulation results indicate that the attenuation range can be reduced to 11-27dB via optimizations. Another circuit presented in this thesis is a current generator for built-in testing of impedance-matched RF front-end circuits with current injection. Since this circuit has high output impedance (>1k up to 2.4GHz), it does not influence the input matching network of the low-noise amplifier (LNA) under test. A major advantage of the current injection method over the typical voltage-mode approach is that the built-in test can expose fabrication defects in components of the matching network in addition to on-chip devices. The current generator was employed together with two power detectors in a realization of a built-in test for a LNA with 14% layout area overhead in 0.13[micron] CMOS technology (<1.5% for the 0.002mm2 current generator). The post-layout simulation results showed that the LNA gain (S21) estimation with the external matching network was within 3.5% of the actual gain in the presence of process-voltage-temperature variations and power detector imprecision. |
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| Item Description: | "Major Subject: Electrical Engineering" Title from author supplied metadata (automated record created 2010-03-12 12:08:51). Electronic resource. |
| Physical Description: | 1 online resource. |
| Bibliography: | Includes bibliographical references. |