Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty.

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This...

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Bibliographic Details

Main Author:	Bahukudumbi, Sudarshan
Other Authors:	Chakrabarty, Krishnendu
Format:	Book
Language:	English
Published:	Boston : Artech House, [2010]
Subjects:	Integrated circuits > Testing. Integrated circuits > Wafer-scale integration. Semiconductors > Testing.