Verification techniques for system-level design /
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as...
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| Format: | eBook |
| Language: | English |
| Published: |
Amsterdam ; Boston :
Morgan Kaufmann Publishers,
[2008]
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| Series: | Morgan Kaufmann series in systems on silicon.
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| Online Access: | Connect to the full text of this electronic book Publisher description |
Internet
Connect to the full text of this electronic bookPublisher description
Available Online
| Call Number: |
TK7895.E42 F95 2008eb |
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| Call Number | Status | Get It |
| TK7895.E42 F95 2008eb | Available | |