Exploiting level sensitive latches in wire pipelining /

Bibliographic Details

Main Author:	Seth, Vikram, 1978-
Other Authors:	Hu, Jiang (Thesis advisor)
Format:	Thesis eBook
Language:	English
Published:	[College Station, Tex.] : [Texas A&M University], [2005]
Subjects:	Major computer engineering. wire delay pipelining signal latency latches
Online Access:	Link to OAK Trust copy