Layout guidelines to minimize latchup in CMOS circuits using guard rings /
This research provides guidelines for selecting, implementing and testing guard structures. To provide these guidelines structural differences of existing guard structures have been explored and the influence of the guard structure layout on CMOS latchup has been investigated. There are only two t...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
2003.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=764878591&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | This research provides guidelines for selecting, implementing and testing guard structures. To provide these guidelines structural differences of existing guard structures have been explored and the influence of the guard structure layout on CMOS latchup has been investigated. There are only two types of guard structures: majority carrier and minority carrier, but there are over twenty-five choices and numerous ways of implementing each choice to minimize latchup. Majority and minority carrier guard structures can be located a) in the substrate, b) near the emitting source, c) surrounding the emitter, d) near the well edge, e) surrounding the well edge, or f) in various positions inside the well. A chip designer must select the appropriate type of guard structure, make decisions to select an appropriate location and determine an optimal guard width for a particular application. The rules for using guard structures are far from universal, and determining which guard structure to implement can be a difficult task for a less experienced designer. The guidelines presented in this research will assist the less experienced designer in making decisions as to which guard structure to select, where to locate the structure within a CMOS layout, and how to test the for latchup immunity of the CMOS design. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | viii, 86 leaves : illustrations ; 28 cm. + 1 CD ROM. Issued also on microfiche from University Microfilm Inc. |
| Bibliography: | Includes bibliographical references (leaves 32-33). |