Layout guidelines to minimize latchup in CMOS circuits using guard rings /

This research provides guidelines for selecting, implementing and testing guard structures. To provide these guidelines structural differences of existing guard structures have been explored and the influence of the guard structure layout on CMOS latchup has been investigated. There are only two t...

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Bibliographic Details

Main Author:	Obiomon, Pamela Holland
Format:	Thesis Book
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 2003.
Subjects:	Major electrical engineering.
Online Access:	http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=764878591&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD