Detection and removal of functional redundancy in multi-level logic circuits /
Whenever digital designs are created, they may contain many logic redundancies. Minimization tools are then used to remove these redundancies. The minimized circuit should be smaller, faster, and cheaper while still behaving like the original circuit. This research will focus on finding non-tradi...
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
2002.
|
| Subjects: | |
| Online Access: | Link to OAK Trust copy |
| Summary: | Whenever digital designs are created, they may contain many logic redundancies. Minimization tools are then used to remove these redundancies. The minimized circuit should be smaller, faster, and cheaper while still behaving like the original circuit. This research will focus on finding non-traditional methods for minimizing multi-level logic circuits. |
|---|---|
| Item Description: | Vita lacking. "Major Subject: Computer Science". |
| Physical Description: | vi, 11 leaves : illustrations ; 28 cm. |
| Bibliography: | Includes bibliographical references (leaves ). |