Detection and removal of functional redundancy in multi-level logic circuits /
Whenever digital designs are created, they may contain many logic redundancies. Minimization tools are then used to remove these redundancies. The minimized circuit should be smaller, faster, and cheaper while still behaving like the original circuit. This research will focus on finding non-tradi...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
2002.
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| Online Access: | Link to OAK Trust copy |
Internet
Link to OAK Trust copyRemote Storage
| Call Number: |
2002 Fellows Thesis D66 |
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| Notes: |
Cushing Archival Copy (Library Use Only) |
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| Call Number | Status | Get It |
| 2002 Fellows Thesis D66 | Available | |
Available Online
| Call Number: |
2002 Fellows Thesis D66 |
|
|---|---|---|
| Call Number | Status | Get It |
| 2002 Fellows Thesis D66 | Available | |