Realistic fault modeling and quality test generation of combined delay faults /

With increasing operating speed and shrinking technology, timing defects in integrated circuits are becoming increasingly important. The well established stuck-at-fault model is not sufficient because it is a static fault model and does not account for the dynamic behavior of the circuit. Due to the...

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Bibliographic Details

Main Author:	Thadhlani, Ajaykumar A.
Format:	Thesis eBook
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 2001.
Subjects:	Major computer engineering.
Online Access:	Link to OAKTrust copy