VLSI implementation of encoder and decoder for low-density parity-check codes /
The aim of this research is to implement an encoder and a message-passing decoder for low-density parity-check codes in hardware. The desired data rate is 44.8 Mbps and the channel is an Additive White Gaussian Noise(AWGN) channel. The effect of using finite precision for the messages passed in de...
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| Format: | Thesis eBook |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
2001.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | The aim of this research is to implement an encoder and a message-passing decoder for low-density parity-check codes in hardware. The desired data rate is 44.8 Mbps and the channel is an Additive White Gaussian Noise(AWGN) channel. The effect of using finite precision for the messages passed in decoding is studied. Optimizations and trade-offs are proposed and implemented to make the hardware small, simple and fast. Performance loss due to optimizations and trade-offs used has been analysed. The implementation has been studied and model implemented for a general purpose Xilinx FPGA XCV-405E. An alternate way to build a decoder at symbol rates is also proposed and a model has been built in VHSIC Hardware Description Language. |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | xi, 85 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references (leaf 84). |