Interconnect testing of embedded memories at chip and system level /
Interconnect testing has become an important aspect for a comprehensive testing of digital system once they are assembled at board/chip level; this has been pioneered by the IEEE through the standard on boundary scan architecture and test access port and its widespread application by the electronic...
| Main Author: | |
|---|---|
| Format: | Thesis Book |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1999.
|
| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=733676321&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | Interconnect testing has become an important aspect for a comprehensive testing of digital system once they are assembled at board/chip level; this has been pioneered by the IEEE through the standard on boundary scan architecture and test access port and its widespread application by the electronic industry. Under this standard, all interconnects on a board/chip must be fully tested to meet stringent requirements such as (A) a small number of vectors; (B) efficient diagnostic capabilities (to include fault location); (C) high coverage of multiple faults. Testing faults in the interconnect of a memory is radically different from the general scenario of a wiring interconnect. The involved functional devices (random access memories) necessitates a different technique as the operations of these devices must be taken into account when generating the test sequence, thus makes the diagnosis problem more difficult. Bus-structured systems are extensively used in current system design due to their efficiency. Testing the bus-structured interconnect also is different from the general wiring interconnect test, and it is more difficult than the general wiring interconnect test. When testing the interconnect faults in bus- connected multi-RAM system, the problem becomes extremely difficult and complicated. To develop efficient diagnosis algorithms and testing strategies is the major issue of this dissertation. This dissertation presents: (1) several novel approaches with different complexity and capability to diagnose the interconnects of a single RAM under a complex fault model; (2) different optimal algorithms to diagnose the bus-structured wiring interconnect under different fault models; (8) the testing strategies and diagnosis algorithms for the bus-connected multi-RAM interconnect test. To achieve maximal diagnosis for a single RAM interconnect test, bus-structured wiring interconnect test and bus-connected multi-RAM interconnect test under general fault model is the major issue and anal goal of this dissertation. Moreover, a novel test operation sequences (for RAM interconnect test) which can save more than one-third of operations than the traditional one is proposed and the reduction technique to simplify the diagnosis on bus-structured system is presented in this dissertation. |
|---|---|
| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xiv, 148 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilm Inc. |
| Bibliography: | Includes bibliographical references (leaves 141-147). |