Bridging faults in CMOS circuits which are non-Iddq testable and their effect on delay testing /
(rather than ratioed logic gates) are investigated.
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1997.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | (rather than ratioed logic gates) are investigated. Bridging defects which occur in CMOS complementary gates create new critical paths through the circuit. Finally, time delay increases and decreases, therefore they can easily domain testing and timing consideration for at speed voltage domain tests are discussed and compared with other testing faults are shown to be the cause of significant transition Iddq testable, but which can be deterministically tested made in this thesis. methods. SPICE level 3 simulations using a technology file provided by Hewlett Packard have verified the observations Realistic bridging defects are shown to exist which are non- using at speed voltage domain (logic) tests. Also. bridging |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | viii, 43 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references: pages 36-38. |