An integrated framework for synthesis for testability /
The work presented in this dissertation proposes a novel framework for design and synthesis applicable in the context of built-in-self-test, BIST, of circuits. This is the first framework which attempts to combine BIST test pattern generation techniques with circuit synthesis-for-test techniques....
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1997.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=739891241&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | The work presented in this dissertation proposes a novel framework for design and synthesis applicable in the context of built-in-self-test, BIST, of circuits. This is the first framework which attempts to combine BIST test pattern generation techniques with circuit synthesis-for-test techniques. In the first part, new techniques for designing test pattern generators for BIST have been developed. Given a circuit under test, CUT, such a test pattern generator can be designed to ensure almost 100% fault coverage. The pattern generator consists of two components: a Generalized LFSR, GLFSR (a pseudo-random pattern generator) and a combinational logic to map the outputs of the pseudo-random pattern generator. The fundamental difference between this technique and weighted pattern generation is that the test pattern generator design can guarantee testing of all hard-to-detect faults without expensive test vector embedding or test point insertion. In the second part, a new logic synthesis method has been introduced which optimizes multi-level circuits simultaneously increasing their testability. The synthesis is based on structural transformations and new transformations using EX-OR gates and Reed Muller expansions have been used. Experiments of the new synthesis algorithms have shown that they can generate circuits with smaller area and test length eliminating many of the hard-to-detect faults. Finally, the proposed methods can be combined to develop an integrated framework providing a more cost effective BIST solution. |
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| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xiii, 133 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references: pages 111-119. |