VLSI yield learning via production functional test data /
Maximizing the slope of the semiconductor manufacturing yield ramp requires rapid failure analysis and continuous monitoring of the fabrication line. At the same time, since metrology is the fastest growing component of fab cost, there is an opposing pressure to eliminate measurements or demonstrat...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=739668241&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | Maximizing the slope of the semiconductor manufacturing yield ramp requires rapid failure analysis and continuous monitoring of the fabrication line. At the same time, since metrology is the fastest growing component of fab cost, there is an opposing pressure to eliminate measurements or demonstrate their benefit. In addition, many defects can only be detected electrically. Direct measurements, such as optical inspection of a test structure, can accurately diagnose problems, but the cost of these techniques is the direct cost of the measurement and the additional inventory cost of wafers undergoing test. Indirect measurements are relatively cheap and fast, and ideal for use during the yield ramp phase, but they require models relating process disturbances to test failures. Our approach to help solve this problem is to build models of how spot defects cause chips to fail, and then we use the models to help determine why chips fail. When chips fail at the tester, information such as the failing vector number, failing test output pattern, IDDQ current, etc., can be recorded at low or no cost. This provides some noisy information on how the chip failed. By combining the test results from a number of chips, we can estimate an ordered defect (Pareto) histogram. The Pareto can be used to prioritize yield improvement activities and detect shifts and drifts in defect densities. We perform the mapping using a probability matrix of defects to faults, and faults to test failures, developed using defect, circuit, and fault simulation. We have shown that slightly modifying the test sequence to gather additional information greatly improves the accuracy of the Pareto. We have also shown that the methodology presented and its results can be used for yield learning in process development. We present a set of criteria that was used to obtain an accurate probability matrix and to collect failure patterns from production test results. The future directions for this work are to study more defect and fault models for a highly accurate probability matrix, and to reduce the CPU time necessary to map from faults to test failures. |
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| Item Description: | Vita. "Major Subject: Computer Science". |
| Physical Description: | xv, 150 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references: pages 117-137. |