Optimal testing for physically-based faults /
In this dissertation) we investigate optimal voltage testing and optimal local time delay testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two fault types: resistive bridges between gate outputs that cause pattern sensi...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=739669461&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | In this dissertation) we investigate optimal voltage testing and optimal local time delay testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two fault types: resistive bridges between gate outputs that cause pattern sensitive functional faults or delay faults, and opens in transmission gates that cause delay faults. In both cases, the traditional stuck-at model local and time delay fault model are inadequate. The test vector to sensitize and propagate a resistive bridging fault is not unique. The traditional greedy test vector selection is optimistic, with some choices having poor real coverage. We realistically model the fault and fault coverage, and describe the optimal selection strategies for voltage testing and delay testing. Bridging faults in CMOS circuits sometimes degrade the output voltage and time performance without altering the logic function. The traditional voltage testing models based on the normal power supply voltage do not accurately model this behavior. In this paper we develop a model of bridging faults that accounts for both the bridging resistance distribution and gate sensitization and propagation choices. This model shows that fault coverage increases at lower power supply voltages. It suggests that decreasing the power supply voltage is a promising technique to maximize the real fault coverage of voltage tests. In a transmission gate with an open NMOS or PMOS device, the output voltage is degraded, increasing delay and reducing noise margin. We model this fault and show how low-voltage testing can be used to detect it. Our goal in applying these techniques is to maximize the real coverage of voltage testing and delay testing, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xi, 89 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references: pages 72-79. |