Improvement of SRAM-based failure analysis calibrated IDDQ testing /
be able to meet with the continuous increasing demand in
| Main Author: | |
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| Format: | Thesis eBook |
| Language: | English |
| Published: |
[Place of publication not identified] :
[publisher not identified] ;
1996.
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| Subjects: | |
| Online Access: | Link to OAKTrust copy |
| Summary: | be able to meet with the continuous increasing demand in cases of certain and uncertain diagnosis. We have causes for yield loss, In this research a methodology to classification under different forms of voltage testing and current testing. In particular we investigate the benefit of dictionary. We investigate the accuracy of the defect effects of unmodeled defects and the ability to identify experimentally validated our approach using a production For any semiconductor industry to be competitive, they should functional test results in combination with a defect-bitmap identify integrated circuit yield detractors using SRAM improve the yields once they are achieved. Yields can be integrated circuit manufacturers try to improve yield to integrated circuits(IC) functionality. Their time-to-market manufacturing cost. Increasing the manufacturing yield will microprocessor cache. normal parametric variations. We also investigate the period should also be optimally small. This necessitates the profitable levels in a short time frame and to maintain or reduce the effective manufacturing cost per die. Hence substantially increased when one is able to identify the usage of sophisticated processing tools that increases the using multiple Iddq current levels calibrated to remove |
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| Item Description: | "Major subject: Electrical Engineering". Vita. |
| Physical Description: | ix, 44 leaves : illustrations ; 28 cm. Also available online. Issued also on microfiche from Lange Micrographics. |
| Bibliography: | Includes bibliographical references. |