A method for finding the critical path in VLSI circuits using the bounded gate delay model /
The procedure for finding an estimate of the critical path delay is referred to as timing analysis. Research in this area has been very active in recent years due to the introduction of increasingly fast VLSI circuits. Delay of a gate is affected by manufacturing process variations and the thermal...
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| Format: | Thesis Book |
| Language: | English |
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[Place of publication not identified] :
[publisher not identified] ;
1995.
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| Online Access: | http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742145181&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD |
| Summary: | The procedure for finding an estimate of the critical path delay is referred to as timing analysis. Research in this area has been very active in recent years due to the introduction of increasingly fast VLSI circuits. Delay of a gate is affected by manufacturing process variations and the thermal and electromagnetic environment. Thus a family of gates that are functionally and topologically identical can have a range of delay values, [D,i,, D,,,,]. This delay model, called the bounded gate delay, has been shown to give the tightest upper bound for the critical delay. This dissertation presents a novel approach for finding the critical path in combinational segments of VLSI circuits using the bounded gate delay. Two types of application dependent path delays are shown to exist. Research by others have assumed only a single type of critical delay. The application of interest here is finding the clock rate of a circuit. Because regular Boolean equations do not contain time information, a new method for representing events with transition uncertainty ranges is proposed. A simple algorithm for simulating logic gates that have delay ranges and handles such signals is also developed. When events with transition uncertainty ranges fan out and reconverge at a later gate, a false static hazard may be produced at the gate output by the gate simulator due to the presence of common ambiguity. A novel way to determine whether a hazard should or should not be produced is also proposed. A static timing analysis algorithm, based the ATPG idea of using mandatory assignments to reduce the search space is proposed. Also developed is a dynamic algorithm that analyzes conflict points to determine if they can be sensitized by applying an event at the conflict points. The method proposed here reduces the search space by first limiting the search to the conflict points, and second by limiting the gate delay values that are considered to those values that could propagate the path event to get to the gate output. |
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| Item Description: | Vita. "Major Subject: Electrical Engineering". |
| Physical Description: | xi, 123 leaves : illustrations ; 28 cm. Issued also on microfiche from University Microfilms Inc. |
| Bibliography: | Includes bibliographical references. |