A method for finding the critical path in VLSI circuits using the bounded gate delay model /

The procedure for finding an estimate of the critical path delay is referred to as timing analysis. Research in this area has been very active in recent years due to the introduction of increasingly fast VLSI circuits. Delay of a gate is affected by manufacturing process variations and the thermal...

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Bibliographic Details

Main Author:	Lee, Jay Hyun, 1955-
Format:	Thesis Book
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 1995.
Subjects:	Major electrical engineering.
Online Access:	http://proxy.library.tamu.edu/login?url=http://proquest.umi.com/pqdweb?did=742145181&sid=1&Fmt=2&clientId=2945&RQT=309&VName=PQD