Design of a multithreaded instruction cache for a hyperscalar processor /

A Multithreaded instruction cache design for a Superscalar architecture supporting the concurrent execution of multiple independent instruction streams, termed as Hyperscalar is presented. The Hyperscalar architecture enhances the instruction issue rate by providing multiple functional units and im...

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Bibliographic Details

Main Author:	Rajagopal, Arjun
Format:	Thesis eBook
Language:	English
Published:	[Place of publication not identified] : [publisher not identified] ; 1993.
Subjects:	Major electrical engineering.
Online Access:	Link to OAKTrust copy