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Formal verification : an essential toolkit for modern VLSI design /

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Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents th...

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Bibliographic Details
Main Author: Seligman, Erik
Corporate Author: ScienceDirect (Online service)
Other Authors: Schubert, Tom, Kumar, M. V. Achutha Kiran
Format: eBook
Language:English
Published: Amsterdam : Elsevier Science, 2015.
Subjects:
Electronic circuits > Testing.
Integrated circuits > Very large scale integration > Design and construction.
Verilog (Computer hardware description language)
Verilog (Langage de description de matériel informatique)
TECHNOLOGY & ENGINEERING > Mechanical.
Electronic circuits > Testing
Integrated circuits > Very large scale integration > Design and construction
Electronic books.
Online Access:Connect to the full text of this electronic book
Description
Summary:Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity.
Item Description:Includes index.
How Do We Reach Targeted Behaviors?
Physical Description:1 online resource (372 pages) : illustrations
ISBN:9780128008157
0128008156