rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Very-Large-Scale Integration Physical Design
    sub title: Engineering Change Order and Timing Design Rule Check
  name:
    name part: Yeap, Kim Ho.
    role:
      role term: creator
  name:
    name part: Tan, Ing Ming.
  type of resource: text
  origin info:
    place:
      place term: enk
    date issued: 2025
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (176 p.)
  abstract: This book presents an innovative approach to rectify Timing-Design Rule Check (TDRC) violations in Very-Large-Scale Integration (VLSI) chip design. Through the utilization of Tool Command Language (TCL) scripting, this automated solution streamlines the Engineering Change Order (ECO) process, offering efficiency, accuracy, and accessibility. By incorporating various strategies such as cell up-sizing, low threshold voltage cell swapping, and buffer insertion, t.
  subject:
    topic: Integrated circuits
    topic: Very large scale integration
  classification: TK7874 .Y43 2025
  classification: 621.395
  related item:
    title info:
      title: Very-Large-Scale Integration Physical Design
    name:
      name part: Yeap, Kim Ho
    origin info:
      publisher: Newcastle-upon-Tyne : Cambridge Scholars Publishing,c2025
  identifier: 9781036440541 (electronic bk.)
  identifier: 1036440540
  location:
    physical location: POD
  record info:
    record content source: EBLCP
    record creation date: 250208
    record change date: 20250810205608.2
    record identifier: in00005657973
    language of cataloging:
      language term: eng