http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Very-Large-Scale Integration Physical Design
Engineering Change Order and Timing Design Rule Check
This book presents an innovative approach to rectify Timing-Design Rule Check (TDRC) violations in Very-Large-Scale Integration (VLSI) chip design. Through the utilization of Tool Command Language (TCL) scripting, this automated solution streamlines the Engineering Change Order (ECO) process, offering efficiency, accuracy, and accessibility. By incorporating various strategies such as cell up-sizing, low threshold voltage cell swapping, and buffer insertion, t.
Newcastle-upon-Tyne : Cambridge Scholars Publishing,c2025