Cover Image

Designing with FPGAs and CPLDs /

Annotation

Bibliographic Details
Main Author: Zeidman, Bob (Author)
Corporate Author: Taylor & Francis
Format: eBook
Language:English
Published: Boca Raton, FL : CRC Press, 2002.
Subjects:
Programmable logic devices.
Embedded computer systems.
Internet.
Internet
Dispositifs logiques programmables.
Systèmes enfouis (Informatique)
Embedded computer systems
Programmable logic devices
Electronic books.
Online Access:Connect to the full text of this electronic book
Table of Contents:
  • Cover
  • Copyright Page
  • Table of Contents
  • Foreword
  • Preface
  • Book Organization
  • Intended Audience
  • Content
  • Support and Feedback
  • Acknowledgments
  • Chapter 1. Prehistory: Programmable Logic to ASICs
  • Objectives
  • 1.1 Programmable Read Only Memories (PROMs)
  • 1.2 Programmable Logic Arrays (PLAs)
  • 1.3 Programmable Array Logic (PALs)
  • 1.4 The Masked Gate Array ASIC
  • 1.5 CPLDs and FPGAs
  • 1.6 Summary
  • Exercises
  • Chapter 2. Complex Programmable Logic Devices (CPLDs)
  • Objectives
  • 2.1 CPLD Architectures
  • 2.2 Function Blocks
  • 2.3 I/O Blocks
  • 2.4 Clock Drivers
  • 2.5 Interconnect
  • 2.6 CPLD Technology and Programmable Elements
  • 2.7 Embedded Devices
  • 2.8 Summary: CPLD Selection Criteria
  • Exercises
  • Chapter 3. Field Programmable Gate Arrays (FPGAs)
  • Objectives
  • 3.1 FPGA Architectures
  • 3.2 Configurable Logic Blocks
  • 3.3 Configurable I/O Blocks
  • 3.4 Embedded Devices
  • 3.5 Programmable Interconnect
  • 3.6 Clock Circuitry
  • 3.7 SRAM vs. Antifuse Programming
  • 3.8 Emulating and Prototyping ASICs
  • 3.9 Summary
  • Exercises
  • Chapter 4. Universal Design Methodology for Programmable Devices
  • Objectives
  • 4.1 What is UDM and UDM-PD?
  • 4.2 Writing a Specification
  • 4.3 Specification Review
  • 4.4 Choosing Device and Tools
  • 4.5 Design
  • 4.6 Verification
  • 4.7 Final Review
  • 4.8 System Integration and Test
  • 4.9 Ship Product!
  • 4.10 Summary
  • Exercises
  • Chapter 5. Design Techniques, Rules, and Guidelines
  • Objectives
  • 5.1 Hardware Description Languages
  • 5.2 Top-Down Design
  • 5.3 Synchronous Design
  • 5.4 Floating Nodes
  • 5.5 Bus Contention
  • 5.6 One-Hot State Encoding
  • 5.7 Design For Test (DFT)
  • 5.8 Testing Redundant Logic
  • 5.9 Initializing State Machines
  • 5.10 Observable Nodes
  • 5.11 Scan Techniques
  • 5.12 Built-In Self-Test (BIST)
  • 5.13 Signature Analysis.