rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Verilog® HDL
    sub title: digital design and modeling
  name:
    name part: Cavanagh, Joseph.
    role:
      role term: creator
  name:
    name part: Taylor & Francis
  type of resource: text
  genre: Electronic books.
  origin info:
    place:
      place term: flu
    place:
      place term: Boca Raton, FL
    publisher: CRC Press
    date issued: ©2007
    date issued: 2007
    issuance: monographic
  language:
    language term: eng
  physical description:
    reformatting quality: preservation
    reformatting quality: access
    form: remote
    extent: 1 online resource (xviii, 890 pages) : illustrations (some color)
  abstract: PREFACE INTRODUCTION History of HDL Verilog HDL IEEE Standard Features Assertion Levels OVERVIEW Design Methodologies Modulo-16 Synchronous Counter Four-Bit Ripple Adder Modules and Ports Designing a Test Bench for Simulation Construct Definitions Introduction to Dataflow Modeling Two-Input Exclusive-OR Gate Four 2-Input AND Gates With Delay Introduction to Behavioral Modeling Three-Input OR Gate Four-Bit Adder Modulo-16 Synchronous Counter Introduction to Structural Modeling Sum-of-Products Implementation Full Adder Four-Bit Ripple Adder Introduction to Mixed-Design Modeling Full Adder Problems LANGUAGE ELEMENTS Comments Identifiers Keywords Bidirectional Gates Charge Storage Strengths CMOS Gates Combinational Logic Gates Continuous Assignment Data Types Module Declaration MOS Switches Multiple-Way Branching Named Event Parameters Port Declaration Procedural Constructs Procedural Continuous Assignment Procedural Flow Control Pull Gates Signal Strengths Specify Block Tasks and Functions Three-State Gates Timing Control User-Defined Primitives Value Set Data Types Net Data Types Register Data Types Compiler Directives Problems EXPRESSIONS Operands Constant Parameter Net Register Bit-Select Part-Select Memory Element Operators Arithmetic Logical Relational Equality Bitwise Reduction Shift Conditional Concatenation Replication Problems GATE-LEVEL MODELING Multiple-Input Gates Gate Delays Inertial Delay.
  abstract: Transport Delay Module Path Delay Additional Design Examples Iterative Networks Priority Encoder Problems USER-DEFINED PRIMITIVES Defining a User-Defined Primitive Combinational User-Defined Primitives Map-Entered Variables Sequential User-Defined Primitives Level-Sensitive User-Defined Primitives Edge-Sensitive User-Defined Primitives Problems DATAFLOW MODELING; Continuous Assignment Three-Input AND Gate Sum Of Products Reduction Operators Octal-To-Binary Encoder Four-To-One Multiplexer Four-To-One Multiplexer Using The Conditional Operator Four-Bit Adder Carry Lookahead Adder Asynchronous Sequential Machine Pulse-Mode Asynchronous Sequential Machine Implicit Continuous Assignment Delays Problems BEHAVIORAL MODELING; Procedural Constructs Initial Statement Always Statement Procedural Assignments Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statement Case Statement Loop Statements For Loop While Loop Repeat Loop Forever Loop Block Statements Sequential Blocks Parallel Blocks Procedural Continuous Assignment Assign ... Deassign Force ... Release Problems STRUCTURAL MODELING Module Instantiation Ports Unconnected Ports Port Connection Rules Design Examples Gray-To-Binary Code Converter BCD-To-Decimal Decoder Modulo-10 Counter Adder/Subtractor Four-Function ALU Adder and High-Speed Shifter Array Multiplier Moore-Mealy Synchronous Sequential Machine Moore Synchronous Sequential Machine Moore Asynchronous.
  abstract: Sequential Machine Moore Pulse-Mode Asynchronous Sequential Machine Problems TASKS AND FUNCTIONS Tasks Task Declaration Task Invocation Functions Function Declaration Function Invocation Problems ADDITIONAL DESIGN EXAMPLES Johnson Counter Counter-Shifter Universal Shift Register Hamming Code Error Detection and Correction Booth Algorithm Moore Synchronous Sequential Machine Mealy Pulse-Mode Asynchronous Sequential Machine Mealy One-Hot Machine BCD Adder/Subtractor BCD Addition BCD Subtraction Pipelined RISC Processor Instruction Cache Instruction Unit Decode Unit Execution Unit Register File Data Cache RISC CPU Top System Top Problems APPENDIX A Event Queue Event Handling for Dataflow Constructs Event Handling for Blocking Assignments Event Handling for Nonblocking Assignments Event Handline for Mixed Blocking and Nonblocking Assignments APPENDIX B Verilog Project Procedure APPENDIX C Answers to Selected Problems Overview Language Elements Expressions Gate Level Modeling User-Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples INDEX.
  table of contents: PREFACE; ; INTRODUCTION; History of HDL; Verilog HDL; IEEE Standard; Features; Assertion Levels; ; OVERVIEW; Design Methodologies; Modulo-16 Synchronous Counter; Four-Bit Ripple Adder; Modules and Ports; Designing a Test Bench for Simulation; Construct Definitions; Introduction to Dataflow Modeling; Two-Input Exclusive-OR Gate; Four 2-Input AND Gates With Delay; Introduction to Behavioral Modeling; Three-Input OR Gate; Four-Bit Adder; Modulo-16 Synchronous Counter; Introduction to Structural Modeling; Sum-of-Products Implementation; Full Adder; Four-Bit Ripple Adder; Introduction to Mixed-Design Modeling; Full Adder; Problems; ; LANGUAGE ELEMENTS; Comments; Identifiers; Keywords; Bidirectional Gates; Charge Storage Strengths; CMOS Gates.
  table of contents: Combinational Logic Gates; Continuous Assignment; Data Types; Module Declaration; MOS Switches; Multiple-Way Branching; Named Event; Parameters; Port Declaration; Procedural Constructs; Procedural Continuous Assignment; Procedural Flow Control; Pull Gates; Signal Strengths; Specify Block; Tasks and Functions; Three-State Gates; Timing Control; User-Defined Primitives; Value Set; Data Types; Net Data Types; Register Data Types; Compiler Directives; Problems; ; EXPRESSIONS; Operands; Constant; Parameter; Net; Register; Bit-Select; Part-Select; Memory Element; Operators; Arithmetic; Logical; Relational; Equality.
  table of contents: Bitwise; Reduction; Shift; Conditional; Concatenation; Replication; Problems; ; GATE-LEVEL MODELING; Multiple-Input Gates; Gate Delays; Inertial Delay; Transport Delay; Module Path Delay; Additional Design Examples; Iterative Networks; Priority Encoder; Problems; ; USER-DEFINED PRIMITIVES; Defining a User-Defined Primitive; Combinational User-Defined Primitives; Map-Entered Variables; Sequential User-Defined Primitives; Level-Sensitive User-Defined Primitives; Edge-Sensitive User-Defined Primitives; Problems; ; DATAFLOW MODELING; Continuous Assignment; Three-Input AND Gate; Sum Of Products; Reduction Operators; Octal-To-Binary Encoder; Four-To-One Multiplexer; Four-To-One Multiplexer Using The Conditional.
  table of contents: Operator; Four-Bit Adder; Carry Lookahead Adder; Asynchronous Sequential Machine; Pulse-Mode Asynchronous Sequential Machine; Implicit Continuous Assignment; Delays; Problems; ; BEHAVIORAL MODELING; Procedural Constructs; Initial Statement; Always Statement; Procedural Assignments; Intrastatement Delay; Interstatement Delay; Blocking Assignments; Nonblocking Assignments; Conditional Statement; Case Statement; Loop Statements; For Loop; While Loop; Repeat Loop; Forever Loop; Block Statements; Sequential Blocks; Parallel Blocks; Procedural Continuous Assignment; Assign ... Deassign; Force ...
  table of contents: Release; Problems; ; STRUCTURAL MODELING; Module Instantiation; Ports; Unconnected Ports; Port Connection Rules; Design Examples; Gray-To-Binary Code Converter; BCD-To-Decimal Decoder; Modulo-10 Counter; Adder/Subtractor; Four-Function ALU; Adder and High-Speed Shifter; Array Multiplier; Moore-Mealy Synchronous Sequential Machine; Moore Synchronous Sequential Machine; Moore Asynchronous Sequential Machine; Moore Pulse-Mode Asynchronous Sequential; Machine; Problems; ; TASKS AND FUNCTIONS; Tasks; Task Declaration; Task Invocation; Functions; Function Declaration; Function Invocation; Problems; ; ADDITIONAL DESIGN EXAMPLES; Johnson Counter; Counter-Shifter; Universal Shift Register; Hamming Code Error Detection and.
  table of contents: Correction; Booth Algorithm; Moore Synchronous Sequential Machine; Mealy Pulse-Mode Asynchronous Sequential Machine; Mealy One-Hot Machine; BCD Adder/Subtractor; BCD Addition; BCD Subtraction; Pipelined RISC Processor; Instruction Cache; Instruction Unit; Decode Unit; Execution Unit; Register File; Data Cache; RISC CPU Top; System Top; Problems; ; APPENDIX A Event Queue; Event Handling for Dataflow Constructs; Event Handling for Blocking Assignments; Event Handling for Nonblocking Assignments; Event Handline for Mixed Blocking and Nonblocking; Assignments; ; APPENDIX B Verilog Project Procedure; ; APPENDIX C Answers to Selected Problems; Overview; Language Elements; Expressions; Gate Level Modeling; User-Defined Primitives; Dataflow Modeling; Behavioral Modeling; Structural.
  table of contents: Modeling; Tasks and Functions; Additional Design Examples; ; INDEX.
  note: Joseph Cavanagh.
  note: Includes index.
  note: Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. http://purl.oclc.org/DLF/benchrepro0212 MiAaHDL
  note: digitized 2011 HathiTrust Digital Library committed to preserve pda MiAaHDL
  note: Includes bibliographical references at the end of each chapters.
  note: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force. WlAbNL
  subject:
    topic: Digital electronics
  subject:
    topic: Logic circuits
    topic: Computer-aided design
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Électronique numérique
  subject:
    topic: Circuits logiques
    topic: Conception assistée par ordinateur
  subject:
    topic: Verilog (Langage de description de matériel informatique)
  subject:
    topic: TECHNOLOGY & ENGINEERING
    topic: Mechanical
  subject:
    topic: Digital electronics
  subject:
    topic: Logic circuits
    topic: Computer-aided design
  subject:
    topic: Verilog (Computer hardware description language)
  subject:
    topic: Électronique numérique
  subject:
    topic: Circuits logiques
    topic: Conception assistée par ordinateur
  subject:
    topic: Verilog (langage de description de matériel informatique)
  classification: TK7868.D5 C395 2007
  classification: 621.39/2
  related item:
    title info:
      title: Verilog HDL
    name:
      name part: Cavanagh, Joseph J.F.
    origin info:
      publisher: Boca Raton, FL : CRC Press, ©2007
    identifier: (DLC) 2006052725
    identifier: (OCoLC)76263541
  identifier: 9781315219547
  identifier: 1315219549
  identifier: 9781420051551
  identifier: 1420051555
  identifier: 1420051547
  identifier: 9781420051544
  identifier: TANDF_188839 Ingram Content Group
  identifier: http://proxy.library.tamu.edu/login
  access condition: Restricted: Printing from this resource is governed by The Legal Deposit Libraries (Non-Print Works) Regulations (UK) and UK copyright law currently in force. WlAbNL
  record info:
    record content source: OCLCE
    record creation date: 110816
    record change date: 20241108165939.7
    record identifier: in00005525098
    language of cataloging:
      language term: eng