Acceleration of biomedical image processing with dataflow on FPGAs /

Short compute times are crucial for timely diagnostics in biomedical applications, but lead to a high demand in computing for new and improved imaging techniques. In this book reconfigurable computing with FPGAs is discussed as an alternative to multi-core processing and graphics card accelerators....

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Bibliographic Details
Main Authors:	Grèull, Frederik (Author), Kebschull, Udo (Author)
Corporate Author:	Taylor & Francis
Format:	eBook
Language:	English
Published:	Gistrup, Denmark : River Publishers, [2016]
Series:	River Publishers series in information science and technology ; v. 22.
Subjects:	Data flow computing. Parallel processing (Electronic computers) Field programmable gate arrays. Image processing > Digital techniques. Flux de données (Informatique) Parallélisme (Informatique) Réseaux logiques programmables par l'utilisateur. Traitement d'images > Techniques numériques. digital imaging. SCIENCE / Energy TECHNOLOGY / Electricity Data flow computing Field programmable gate arrays Image processing > Digital techniques Electronic books.
Online Access:	Connect to the full text of this electronic book

Table of Contents:

Foreword xi
Preface xiii
Acknowledgments xv
List of Figures xvii
List of Tables xxi
List of Listings xxiii
List of Abbreviations xxv
1 Introduction 1
1.1 Motivation 1
1.2 Overview 2
1.2.1 The Idea 2
1.2.2 Aim of this Book 3
1.3 Outline 5
2 Dataflow Computing 7
2.1 Early Approaches 7
2.1.1 Control Flow and Dataflow 7
2.1.2 Dataflow Machines 9
2.1.3 Dataflow Programs 11
2.2 Principles of Dataflow Computing on Reconfigurable Hardware 12
2.2.1 Primitives 13
2.2.2 Scheduling 15
2.2.2.1 Dynamic scheduling 15
2.2.2.2 Static scheduling 15
2.2.2.3 Combined forms 16
2.2.3 Image Processing 16
2.2.3.1 Point operations 16
2.2.3.2 Convolutions 17
2.2.3.3 Reductions 18
2.2.3.4 Operations with non-linear access patterns 18
2.3 FPGA Hardware 19
2.3.1 Integrated Circuits 19
2.3.1.1 Configurable logic blocks 20
2.3.1.2 Block RAM 21
2.3.1.3 Digital signal processors 22
2.3.2 Low-Level Hardware Description Languages 23
2.3.2.1 VHDL and Verilog 23
2.3.2.2 FPGA design flow 25
2.3.3 FPGAs as Application Accelerators 26
2.3.3.1 Pipelining 28
2.3.3.2 Flynn's taxonomy 30
2.3.3.3 Limits of acceleration 31
2.4 Languages 32
2.4.1 Imperative Languages 34
2.4.1.1 Handel-C 34
2.4.1.2 Xilinx Vivado high-level synthesis 35
2.4.1.3 ROCCC 2.0
36
2.4.2 Stream Languages 37
2.4.2.1 MaxCompiler 38
2.4.2.2 Silicon Software VisualApplets 40
3 Acceleration of Imperative Code with Dataflow Computing 43
3.1 Relation to List Processing 43
3.1.1 Basic Functions 46
3.1.2 Transformations 47
3.1.2.1 Nested lists 48
3.1.3 Reductions 49
3.1.4 Generation 50
3.1.5 Sublists 51
3.1.6 Searching 53
3.1.6.1 Indexing lists 54
3.1.7 Zipping and Unzipping 54
3.1.8 Set Operations 55
3.1.9 Ordered Lists 56
3.1.10 Summary 57
3.2 Identification of Throughput Boundaries 57
3.2.1 Profiling in Software 59
3.2.2 Profiling the CPU System 61.
3.2.3 Profiling Dataflow Designs 62
3.3 Pipelining Imperative Control Flows 63
3.3.1 Sequences 66
3.3.2 Conditionals 68
3.3.3 Loops 71
3.3.3.1 Loop unrolling 72
3.3.3.2 Loop parallelization 73
3.3.3.3 Loop cascading 76
3.3.3.4 Loop tiling 79
3.3.3.5 Loop interweaving 83
3.3.3.6 Finite-state machines 83
3.3.4 Summary 84
3.4 Efficient Bit and Number Manipulations 85
3.4.1 Encoding 85
3.4.1.1 Integers and fixed-point representations 86
3.4.1.2 Floating-point representations 88
3.4.1.3 Alternative encodings 90
3.4.2 Dimensioning 91
3.4.2.1 Range 92
3.4.2.2 Precision 93
3.5 Customizing Memory Access 95
3.5.1 Memory Layout and Access Patterns 97
3.5.2 On-Chip Memory 97
3.5.3 Off-Chip Memory 98
3.6 Summary 99
4 Biomedical Image Processing and Reconstruction 101
4.1 Localization Microscopy 101
4.1.1 History 102
4.1.2 Physical Principles 105
4.1.3 Localization Algorithms 108
4.1.4 Background Removal 109
4.1.5 Spot Detection 112
4.1.6 Feature Extraction 114
4.1.7 Super-Resolution Image Generation 119
4.1.8 State of the Art 120
4.1.9 Analysis of the Algorithm 122
4.1.9.1 Methods 123
4.1.9.2 Dataflow 125
4.1.9.3 Dimensioning of the hardware 127
4.1.10 Implementation 129
4.1.10.1 Host code 130
4.1.10.2 Background removal 130
4.1.10.3 Spot detection 131
4.1.10.4 Spot separation 133
4.1.10.5 Feature extraction 134
4.1.10.6 Visualization 135
4.1.11 Results 136
4.1.11.1 Accuracy 136
4.1.11.2 Throughput 141
4.1.11.3 Resource usage 143
4.1.12 Discussion 144
4.2
3D Electron Tomography 145
4.2.1 Reconstruction Algorithms 147
4.2.2 State of the Art 149
4.2.3 Analysis of the Algorithm 151
4.2.3.1 Modifications 151
4.2.3.2 Dataflow 155
4.2.3.3 Dimensioning of the hardware 157
4.2.4 Implementation 160
4.2.4.1 Scheduling 161
4.2.4.2 External DRAM 164
4.2.4.3 Ray-Box intersection 165
4.2.4.4 Projection accumulator 165.
4.2.4.5 Residues storage 169
4.2.4.6 Multi-piping 170
4.2.5 Results 171
4.2.5.1 Accuracy 172
4.2.5.2 Throughput 173
4.2.5.3 Resource usage 175
4.2.6 Discussion 176
5 Conclusion 179
5.1 Portability 179
5.2 High-Level Development 180
5.3 Acceleration 181
5.4 Outlook 182
References 185
Index 197
About the Authors 199.