http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
Testing for small-delay defects in nanoscale CMOS integrated circuits
1 online resource (xv, 247 pages) : illustrations
Advances in design methods and process technologies have resulted in a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits covers common problems in areas such as process variations, power supply noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DfM)-related rule violations. The book also addresses testing for small-delay.
Section 1. Timing-aware ATPG -- section 2. Faster-than-at-speed -- section 3. Alternative methods -- section 4. SDD metrics.
edited by Sandeep K. Goel, Krishnendu Chakrabarty.
Includes bibliographical references and index.
Metal oxide semiconductors, Complementary