System level design with .NET technology /
| Corporate Author: | |
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| Other Authors: | , |
| Format: | eBook |
| Language: | English |
| Published: |
Boca Raton :
CRC Press,
2018.
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| Edition: | 1st |
| Subjects: | |
| Online Access: | Connect to the full text of this electronic book |
| Item Description: | Previously issued in print: 2009. <P>Introduction</P><P>Needs of a complete and efficient design environment </P><P>Design flow with ESys.NET </P><P>Simulation flow with ESys.NET </P><P>Observer based verification flow with ESys.NET </P><P>Conclusion and book organization </P><P>References </P><P>Part I: MODELING AND SPECIFICATION</P><P>l. H-level requirements engineering for electronic system-level design</P><P>1.1. Introduction</P><P>1.2. Background</P><P>1.2.1 Framework</P><P>1.2.2 Software Engineering Approaches</P><P>1.3. Proposed Solution</P><P>1.3.1 Formalism</P><P>1.3.2 Linguistic Pre-Processing</P><P>1.3.3 Consistency Validation</P><P>1.3.4 Elicitation of Missing Functionalities</P><P>1.4. Experimental Results</P><P>1.4.1 Automatic Door Controller</P><P>1.4.2 Industrial Router</P><P>1.4.3 RapidIO</P><P>1.5. Linking to a UML-Based Methodology</P><P>1.5.1 Integrated Methodology</P><P>1.5.2 Case Study</P><P>1.6. Conclusion</P><P>2. Transaction Level Modeling with .Net</P><P>2.1. Introduction</P><P>2.2. Transaction Level Modeling</P><P>2.3. Abstract Model</P><P>2.4. XML Abstract Model Representation</P><P>2.5. Simulation Model Generation</P><P>2.6. TLM Expression with .NET</P><P>2.7. Conclusion</P><P>3. Matching Design Patterns Concepts with Hardware Concepts</P><P>3.1. Introduction</P><P>3.2. Related Work & Background</P><P>3.2.1 Original Patterns</P><P>3.2.2 Patterns and Hardware</P><P>3.3. Patterns and our Classification System</P><P>3.4. Object-Oriented Translations</P><P>3.4.1 Translations of Object Properties</P><P>3.4.2 Translations of Object Methods</P><P>3.4.3 Translations of Polymorphism</P><P>3.5. Constraints and Assumptions</P><P>3.5.1 Constraint: Dynamism of the Hardware</P><P>3.5.2 Assumptions: Pattern Automatic Recognition Problem</P><P>3.6. Design Pattern Mappings</P><P>3.6.1 Creational Patterns</P><P>3.6.2 Structural Patterns</P><P>3.6.3 Behavioral Patterns</P><P>3.7. Conclusion</P><P>PART II: SIMULATION</P><P>4. A Service Oriented Simulation framework Using .Net Technologies</P><P>4.1. Introduction</P><P>4.2. Earlier versions of ESyS.Net</P><P>4.3. SoCML</P><P>4.3.1 Separation of Concerns</P><P>4.3.2 Service Oriented Modeling Language</P><P>4.3.3 MOC Modeling</P><P>4.4. ESyS.Net 3</P><P>4.4.1 Model Elaboration</P><P>4.4.2 Simulation Core</P><P>4.5. Conclusion</P><P>5. Co-simulation of Multi-Language Descriptions of Heterogeneous Systems </P><P>5.1. Introduction </P><P>5.2. Methods Overview for Co-simulation </P><P>5.2.1 TCP/IP </P><P>5.2.2 Shared Memory </P><P>5.2.3 Pinvoke DLL </P><P>5.2.4 Component Object Model (COM) </P><P>5.2.5 Static Function </P><P>5.2.6 The Managed Wrapper </P><P>5.3. Simulation of Multi-Language Descriptions of Heterogeneous Systems </P><P>5.3.1 Simulation Flow </P><P>5.3.2 RTL level </P><P>5.3.3 TLM level </P><P>5.3.4 Example for Compiled Model </P><P>5.3.5 Comparison between New Methodologies and Standard Co-Simulation</P><P>5.4. Conclusion </P><P>PART III VERIFICATION</P><P>6. Implementing LTL Based Verification Through Reflection</P><P>6.1. Introduction</P><P>6.2. Conclusion</P><P>7. Timing Constraints Verification</P><P>7.1. Introduction</P><P>7.2. Timing Specification</P><P>7.3. MiniMax Timing Specification</P><P>7.4. Realizability of Min/Max Timing Specification</P><P>7.5. TLM and Timing in TLM</P><P>7.6. Conclusion</P><P>8. Extension of Esys.net by System Verilog Assertions</P><P>8.1. Introduction</P><P>8.2. Representing System Verilog Assertions 3.1 in HOL </P><P>8.2.1 The HOL System </P><P>8.2.2 Representing Letters and Words in HOL </P><P>8.2.3 Representing Syntax in HOL </P><P>8.2.4 Formal Semantics in HOL </P><P>8.2.5 Proofs in HOL </P><P>8.2.6 Mapping from SVA 3.1 to PSL 1.1. </P><P>8.3. Translating SVA to w-Automata in HOL</P><P>804. Integration of Verification Environment based in SVA in Esys.net</P><P>8.5. Conclusion </P><P>PART VI: SYNTHESIS AND IMPLEMENTATION</P><P>9. OS Space Exploration and Software Synthesis</P><P>9.1. Introduction</P><P>9.2. OS Selection</P><P>9.3. OS Services' Refinement</P><P>9 A. Writing Modem and Portable OS</P><P>9.5. Abstracting the OS</P><P>9.6. Conclusion</P><P>10. Design and Implementation of a CIL Processor for Embedded Applications </P><P>10.1. Introduction </P><P>10.2. The Conception of Micro-Architecture, Micro-Program and Micro-Instructions</P><P>10.3. An Implementation of Micro-Architecture for CIL </P><P>10.3.1 CIL and SCIL </P><P>10.3.2 Micro-program (Micro-Instructions) for this Implementation </P><P>10.3.3 The Architecture of CIL processor </P><P>10.3.4 Performance </P><P>11. Conclusion </P><P>References</P><P>Index</P> |
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| Physical Description: | 1 online resource |
| Bibliography: | Includes bibliographical references and index. |
| ISBN: | 9781351834063 1351834061 9781439812129 1439812128 9781351825375 1351825372 9781315218175 1315218178 |