rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Real-time expert systems computer architecture
  name:
    name part: Hodson, R. F.
    role:
      role term: creator
  name:
    name part: Taylor & Francis
  type of resource: text
  genre: bibliography
  genre: Electronic books.
  origin info:
    place:
      place term: xx
    place:
      place term: Milton
    publisher: CRC Press
    date issued: 2018
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (301 pages)
  abstract: Expert systems and real-time systems technology have been developed independently. Expert systems have been successfully implemented in many complex applications traditionally performed by human experts. Real-time systems have been successfully applied in areas requiring interaction with dynamic environments, control and monitoring applications for example. Merging these two technologies will yield intelligent systems capable of interacting with complex dynamic environments, an area in which human operators exhibit poor productivity, due to cognitive overload.
  table of contents: Cover; Title Page; Copyright Page; Dedication; PREFACE; THE AUTHORS; Table of Contents; 1: Real-Time Expert Systems; 1.1 Expert Systems; 1.2 Real-Time Systems; 1.3 Why Real-Time Expert System?; 1.4 Existing Architectures; 1.4.1 von Neumann Architectures; 1.4.2 Dataflow Architectures; 1.4.3 Multiprocessor Systems; 1.5 Systems Requirements; 1.5.1 Timing; 1.5.2 Procedural & Declarative Representations; 1.5.3 Uncertainty; 1.5.4 Environment Interface; 1.5.5 Hierarchical Organization; 1.6 Summary; 2: System Design; 2.1 Topology; 2.2 Processor Structure; 2.2.1 Interference Mechanism
  table of contents: 2.2.2 Dataflow Methodology2.2.3 Priority; 2.2.4 Uncertainty Processing; 2.2.5 External Interface; 2.2.6 Temporal Data; 2.2.7 Procedural Data; 2.2.8 Communication; 2.2.9 Dynamic Memories; 2.3 Summary; 3: System Implementation; 3.1 ARL Implementation; 3.1.1 ARL Control; 3.1.2 ARL Interfaces; 3.1.3 Memory Address Hardware; 3.1.4 Rule Memory; 3.1.5 ARL Memory; 3.1.6 Memory Register; 3.1.7 Decrement Logic; 3.1.8 Link Priority Logic; 3.1.9 Negation Logic; 3.1.10 Min/Max Logic; 3.1.11 ARL Microcode; 3.2 APQ Implementation; 3.2.1 APQ Control; 3.2.2 APQ Interfaces; 3.2.3 APQ Priority Logic
  table of contents: 3.2.4 APQ Memory Organization3.2.5 APQ Register File; 3.2.6 APQ Free Register and Pointer Buffer; 3.2.7 APQ Empty Queue Logic; 3.2.8 APQ Microcode; 3.3. CPQ Implementation; 3.3.1 CPQ Microcode; 3.4 AP Implementation; 3.4.1 AP Control; 3.4.2 AP Interfaces; 3.4.3 Antecedent Memory; 3.4.4 Antecedent Compare Hardware; 3.4.5 Wait List Memory; 3.4.6 AP Microcode; 3.5 CP Implementation; 3.5.1 CP Code; 3.6 WM Implementation; 3.7 Message Buffer Implementation; 3.8 External Interface Implementation; 3.9 Real-Time Clock Implementation; 3.10 System Reset Implementation; 3.11 Clock Distribution
  table of contents: 3.12 Summary4: System Simulation; 4.1 Simulation Goals; 4.2 Simulation Approach; 4.2.1 Discrete-Event Simulation; 4.2.2 Process Concept; 4.2.3 Resource Concept; 4.2.4 Process-Resource Example; 4.2.5 Program Structure; 4.2.6 Simulation Model; 4.3 Simulation Results; 4.3.1 Peak & Typical Processing Rates; 4.3.2 Effect of ICUs; 4.3.3 Effect of Tasks; 4.3.4 Effect of Pruning; 4.4 Conclusion; Bibliography; A: Hardware Diagrams; A.1 ARL Hardware; A.2 APQ Hardware; A.3 CPQ Hardware; A.4 AP Hardware; A.5 CP Hardware; A.6 WM Hardware; A.7 MB Hardware; A.8 External Interface Hardware
  table of contents: A.9 Real-Time Clock HardwareA. 10 System Reset Hardware; A.11 Clock Generation Hardware; B: Sequencer and Microprocessor Code; B.1 ARL Microcode; B.1.1 Microbit Definitions; B.1.2 Test Bit Definitions; B.1.3 Microcode Description; B.2 APQ Microcode; B.2.1 Microbit Definition; B.2.2 Test Bit Definition; B.2.3 Microcode Description; B.3 CPQ Microcode; B.3.1 Microbit Definition; B.3.2 Test Bit Definition; B.3.3 Microcode Description; B.4 AP Microcode; B.4.1 Microbit Definition; B.4.2 Test Bit Definition; B.4.3 Microcode Description; B.5 CP Code; B.5.1 CP Address Map
  note: Robert F. Hodson, Abraham Kandel.
  note: B.5.2 CP Code Segment Descriptions
  note: Includes bibliographical references and index.
  subject:
    topic: Expert systems (Computer science)
  subject:
    topic: Real-time data processing
  subject:
    topic: Computer architecture
  subject:
    topic: Expert Systems
  subject:
    topic: Systèmes experts (Informatique)
  subject:
    topic: Temps réel (Informatique)
  subject:
    topic: Ordinateurs
    topic: Architecture
  subject:
    topic: COMPUTERS
    topic: General
  subject:
    topic: Computer architecture
  subject:
    topic: Expert systems (Computer science)
  subject:
    topic: Real-time data processing
  classification: QA76.76.E95 H53 2018eb
  classification: 006.3/3
  related item:
    title info:
      title: Real-Time Expert Systems Computer Architecture
    name:
      name part: Hodson, R.F.
    origin info:
      publisher: Milton : CRC Press, ©2018
  identifier: 9781351093101
  identifier: 135109310X
  identifier: 9781351076203
  identifier: 1351076205
  identifier: 9781351084659
  identifier: 1351084658
  identifier: 9781315897103
  identifier: 9781351093101 Ingram Content Group
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: EBLCP
    record creation date: 180127
    record change date: 20241108165729.7
    record identifier: in00005522188
    language of cataloging:
      language term: eng