| Abstract: | Analog Integrated Circuit (IC) layout design is typically a labor-intensive process that requires strong human intervention and trial-and-error iterations. Although automated analog layout has been studied for decades, there are still significant performance gaps compared with manual lay-out. This thesis contributes four machine learning (ML)-based technical solutions for performance driven analog IC layout, aiming at bridging the performance gaps and reducing human efforts. Analog circuit performance is sensitive to layout parasitic. Placement is thus important as the distance among pins decides the first-order effect on layout parasitic. However, most of the previous placement works are focused on special geometric constraints, such as symmetry and common-centroid. Limited work directly optimizes circuit performance in placement. We propose to use ML techniques to achieve performance driven placement, where ML models are incorporated with an analog placer to optimize circuit performance directly during the placement iterations. The training is performed using a pre-routing estimate based on the star model. Experiment results show that it could reach performance similar to manual layout but is orders of magnitude faster. An analog circuit and its placement can be encoded into a graph, where the circuit performance is not only related to circuit topology but also features inside the graph. Graph Neural Network (GNN) is superior for graph data in capturing the topology and more efficient in feature encoding. Instead of plug-in use of existing ML techniques, we propose a customized graph neural network, Pooling with Edge Attention (PEA) Network. It incorporates Graph Attention Network (GAT) and DiffPool as key ingredients. Benefited by its new feature edge-based attention and edge pooling, knowledge obtained by a PEA network can be transferred among different topologies of the same circuit type. Simulation results show that PEA improves 8.7% accuracy compared to a recent Convolutional Neural Network (CNN)-based model. It is further applied to guide analog placement and achieves performance similar to manual designs. Transistor sizing is an early design step to determine circuit performance. However, many previous works mean to perform sizing for schematic designs prior to layout. Thus layout effects are failed to be captured in their works. We use reinforcement learning to find robust sizing solutions against performance uncertainty due to layout effects. A circuit attention network technique is developed to capture the impact of transistor sizing on circuit performance in an actor-critic learning framework. Our approach also includes a stochastic technique for addressing layout effects. Compared to Bayesian optimization (BO) and Graph Convolutional Network-based reinforcement learning (GCN-RL), two state-of-the-art methods, the proposed approach can achieve 10.6% performance improvement or at least 5.6©₇ speed up. Wire sizes play a significant role on the layout RC parasitic. However, performance driven wire sizing for analog ICs has received very little research attention. To fill this void, we develop several techniques to facilitate an end-to-end automatic wire sizing approach. They include a circuit performance model based on customized GNN and two optimization techniques: one is Bayesian optimization accelerated by the GNN model and the other is based on TensorFlow training. Experimental results show that our best technique can achieve 11% circuit performance improvement or 8.7©₇ speedup compared to a conventional BO method. The electronic version of this dissertation is accessible from https://hdl.handle.net/1969.1/198007 |
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