rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Modern receiver front-ends
    sub title: systems, circuits, and integration
  name:
    name part: Laskar, Joy.
    role:
      role term: creator
  name:
    name part: Matinpour, Babak.
  name:
    name part: Chakraborty, Sudipto.
  type of resource: text
  genre: bibliography
  genre: Electronic books.
  origin info:
    place:
      place term: nju
    place:
      place term: Hoboken, N.J.]
    publisher: Wiley-Interscience
    date issued: ©2004
    date issued: 2004
    issuance: monographic
  language:
    language term: eng
  physical description:
    form: remote
    extent: 1 online resource (xiii, 221 pages) : illustrations
  abstract: Architectures BABAK MATINPOUR and JOY LASKAR* Describes the actual implementation of receiver architectures from the initial design to an IC-based product* Presents many tricks-of-the-trade not usually covered in textbooks* Covers a range of practical issues including semiconductor technology selection, cost versus performance, yield, packaging, prototype development, testing, and analysis* Discusses architectures that are employed in modern broadband wireless systems.
  table of contents: MODERN RECEIVER FRONT-ENDS; CONTENTS; Preface; Acknowledgments; 1 INTRODUCTION; 1.1 Current State of the Art; 2 RECEIVER SYSTEM DESIGN; 2.1 Frequency Planning; 2.1.1 Blockers; 2.1.2 Spurs and Desensing; 2.1.3 Transmitter Leakage; 2.1.4 LO Leakage and Interference; 2.1.5 Image; 2.1.6 Half IF; 2.2 Link Budget Analysis; 2.2.1 Linearity; 2.2.2 Noise; 2.2.3 Signal-to-Noise Ratio; 2.2.4 Receiver Gain; 2.3 Propagation Effects; 2.3.1 Path Loss; 2.3.2 Multipath and Fading; 2.3.3 Equalization; 2.3.4 Diversity; 2.3.5 Coding; 2.4 Interface Planning; 2.5 Conclusion; 3 REVIEW OF RECEIVER ARCHITECTURES
  table of contents: 3.1 Heterodyne Receivers3.2 Image Reject Receivers; 3.2.1 Hartley Architecture; 3.2.2 Weaver Architecture; 3.3 Zero IF Receivers; 3.4 Low IF Receivers; 3.5 Issues in Direct Conversion Receivers; 3.5.1 Noise; 3.5.2 LO Leakage and Radiation; 3.5.3 Phase and Amplitude Imbalance; 3.5.4 DC Offset; 3.5.5 Intermodulations; 3.6 Architecture Comparison and Trade-off; 3.7 Conclusion; 4 SILICON-BASED RECEIVER DESIGN; 4.1 Receiver Architecture and Design; 4.1.1 System Description and Calculations; 4.1.2 Basics of OFDM; 4.1.3 System Architectures; 4.1.4 System Calculations; 4.2 Circuit Design
  table of contents: 4.2.1 SiGe BiCMOS Process Technology4.2.2 LNA; 4.2.3 Mixer; 4.2.4 Frequency Divider; 4.3 Receiver Design Steps; 4.3.1 Design and Integration of Building Blocks; 4.3.2 DC Conditions; 4.3.3 Scattering Parameters; 4.3.4 Small-Signal Performance; 4.3.5 Transient Performance; 4.3.6 Noise Performance; 4.3.7 Linearity Performance; 4.3.8 Parasitic Effects; 4.3.9 Process Variation; 4.3.10 50-W and Non-50-W Receivers; 4.4 Layout Considerations; 4.5 Characterization of Receiver Front-Ends; 4.5.1 DC Test; 4.5.2 Functionality Test; 4.5.3 S-Parameter Test; 4.5.4 Conversion Gain Test; 4.5.5 Linearity Test
  table of contents: 4.5.6 Noise Figure Test4.5.7 I/Q Imbalance; 4.5.8 DC Offset; 4.6 Measurement Results and Discussions; 4.6.1 Close Examination of Noise Figure and I/Q Imbalance; 4.6.2 Comments on I/Q Imbalance; 4.7 Conclusion; 5 SUBHARMONIC RECEIVER DESIGNS; 5.1 Illustration of Subharmonic Techniques; 5.2 Mixing Using Antisymmetric I-V Characteristics; 5.3 Impact of Mismatch Effects; 5.4 DC Offset Cancellation Mechanisms; 5.4.1 Intrinsic DC Offset Cancellation; 5.4.2 Extrinsic DC Offset Cancellation; 5.5 Experimental Verification of DC Offset; 5.6 Waveform Shaping Before Mixing; 5.6.1 Theory and Analysis
  table of contents: 5.6.2 Experimental Verification on GaAs MESFET APDP5.6.3 Implementation in Silicon; 5.7 Design Steps for APDP-Based Receivers; 5.8 Architectural Illustration; 5.9 Fully Monolithic Receiver Design Using Passive APDP Cores; 5.9.1 Integrated Direct Conversion Receiver MMIC's; 5.9.2 Receiver Blocks; 5.9.3 Additional Receiver Blocks; 5.10 Reconfigurable Multiband Subharmonic Front-Ends; 5.11 Conclusion; 6 ACTIVE SUBHARMONIC RECEIVER DESIGNS; 6.1 Stacking of Switching Cores; 6.1.1 Description and Principles; 6.1.2 Subharmonic Receiver Architecture; 6.2 Parallel Transistor Stacks; 6.2.1 Active Mixer
  note: Joy Laskar, Babak Matinpour, Sudipto Chakraborty.
  note: Includes bibliographical references and index.
  subject:
    topic: Radio frequency integrated circuits
  subject:
    topic: Radio
    topic: Receivers and reception
    topic: Design and construction
  classification: TK7874.78 .L37 2004eb
  classification: 621.384/18
  classification: 621.396.62
  related item:
    title info:
      title: Modern receiver front-ends
    name:
      name part: Laskar, Joy.
    origin info:
      publisher: [Hoboken, N.J.] : Wiley-Interscience, ©2004
    identifier: (DLC) 2003019188
  identifier: 047147486X
  identifier: 9780471474869
  identifier: 0471225916
  identifier: 9780471225911
  identifier: 0471474851
  identifier: 9780471474852
  identifier: OverDrive, Inc.
  identifier: 69059068-DC0A-4CD1-B85B-21094213B2C7 OverDrive, Inc.
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: NhCcYBP
    record creation date: 040412
    record change date: 20260214234402.8
    record identifier: in00004678990
    language of cataloging:
      language term: eng