Cover Image

Microcontroller and Smart Home Networks.

Show other versions (1)
Bibliographic Details
Main Author: Dawoud, Dawoud Shenouda
Corporate Author: ProQuest (Firm)
Other Authors: Dawoud, Peter
Format: eBook
Language:English
Published: Aalborg : River Publishers, 2020.
Series:River Publishers Series in Communications Ser.
Subjects:
Home automation.
Electronic books.
Online Access:Connect to the full text of this electronic book
Table of Contents:
  • Front Cover
  • Microcontroller and Smart: ptHome Networks
  • Contents
  • Preface
  • Acknowledgment
  • List of Figures
  • List of Tables
  • List of Abbreviations
  • Section I: Inter-integrated Circuits (IIC)
  • 1 Inter-integrated Circuits (IIC/I2C)
  • 1.1 Introduction
  • 1.1.1 I2C Revisions
  • 1.2 I2C Bus Terminology
  • 1.3 I2C Protocol
  • 1.3.1 Transaction Format-Message Format
  • 1.3.2 Timing Diagram
  • 1.4 The I2C Bus Hardware Structure
  • 1.4.1 Electrical Consideration
  • 1.4.1.1 Types of devices that can be connected to I2C bus
  • 1.4.1.2 Electrical considerations that limits I2C bus length
  • 1.5 The Physical Bus-I2C Bus Interface
  • 1.6 SDA and SCL Signals
  • 1.7 Masters and Slaves
  • 1.7.1 Buffering and Multiplexing
  • 1.8 I2C Data Validity
  • 1.9 Voltage Levels and Resistor Values
  • 1.10 Start/Stop Sequence
  • 1.11 Repeated START Condition
  • 1.12 Addressing Structure
  • 1.12.1 7-bit Addressing
  • 1.12.2 Acknowledge Scheme
  • 1.12.3 I2C Addresses Standard: 10-bit Addressing
  • 1.12.3.1 I2C bus transactions in case of 10-bit address
  • 1.12.4 I2C Addresses Standard: Special Addresses and Exceptions in 7-bit Address Space
  • 1.12.4.1 Reserved and none-reserved addresses in 7-bit address space
  • 1.12.4.1.1 Reserved addresses in 7-bit address space
  • 1.12.4.2 Non-reserved addresses in 7-bit address space
  • 1.13 I2C Bus Transaction
  • 1.13.1 I2C Bus Events 1: Master (Transmitter) to Slave (Receiver) Data Transfer
  • 1.13.2 I2C Bus Events 2: Slave (Transmitter) to Master (Receiver) Data Transfer
  • 1.13.3 I2C Bus Events 3: Bidirectional Read and Write in Same Data Transfer
  • 1.14 Clock Stretching
  • 1.15 Possible Modifications on the Timing Diagram
  • 1.16 Bus Clear
  • 1.17 Applicability of I2C Bus Features
  • 1.18 I2C Modes: Bus Speeds
  • 1.18.1 Low-speed Mode or Standard Mode
  • 1.18.2 Enhanced I2C (Fast Mode)
  • 1.18.3 Fast-mode plus (FM+)
  • 1.18.4 High-speed Mode (HS mode)
  • 1.18.4.1 Electrical characteristics of HS mode
  • 1.18.4.2 Transmission format of high-speed mode
  • 1.18.5 Ultra-fast Mode (UFm)
  • 1.19 I2C as a Multi-master Bus: Bus Arbitration
  • 1.19.1 Arbitration
  • 1.19.2 Bus Monitoring
  • 1.19.3 Possibility of Collision
  • 1.19.4 Clock Synchronization and Handshaking
  • 1.19.4.1 Clock synchronization
  • 1.19.4.2 Handshaking: Using the clock synchronizing mechanism as a handshake
  • 1.20 I2C Interface: Connecting I2C Bus to a PC
  • 2 Design of I2C Bus and Operation
  • 2.1 Design of I2C Bus
  • 2.1.1 Open-drain Lines
  • 2.1.1.1 Open-drain for Bidirectional Communication
  • 2.1.2 Calculation of the Pull-up Resistor
  • 2.1.2.1 Supply voltage (Vcc)
  • 2.1.2.2 Total bus capacitance (CBUS or Cb) and Rp(max)
  • 2.1.2.3 Total high-level input current (IIH): Input leakage
  • 2.1.2.4 Bus speed versus power consumption
  • 2.1.3 Maximum Clock Frequency of I2C Bus