rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Introduction to SystemVerilog
  name:
    name part: Mehta, Ashok B.
    role:
      role term: creator
    role:
      role term: author.
    role:
      role term: aut
    role:
      role term: http://id.loc.gov/vocabulary/relators/aut
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  genre: Electronic books.
  origin info:
    place:
      place term: gw
    date issued: 2021
    edition: 1st ed. 2021.
    issuance: monographic
  language:
    language term: eng
  physical description:
    reformatting quality: access
    form: remote
    extent: 1 online resource (XXXV, 852 pages 156 illustrations, 148 illustrations in color.)
  abstract: This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Syst…
  table of contents: Introduction -- Data Types -- Arrays -- Queues -- Structures -- Packages -- Class -- SystemVerilog 'module' -- SystemVerilog 'program' -- Interfaces -- Operators -- Constrained Random Test Generation and Verification -- SystemVerilog Assertions -- Functional Coverage -- SystemVerilog Processes -- Procedural programming statements -- Processes -- Tasks and Functions -- Clocking Blocks -- Checkers -- Inter-process communication and synchronization -- Utility System tasks and functions.
  note: by Ashok B. Mehta.
  subject:
    topic: Electronic circuits
  subject:
    topic: Microprocessors
  subject:
    topic: Circuits and Systems
  subject:
    topic: Processor Architectures
  classification: TK7888.4
  classification: 621.3815
  related item:
    title info:
      title: Springer Nature eBook
  identifier: 9783030713195
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record creation date: 210706
    record change date: 20230330185334.2
    record identifier: in00004387084