Analysis and Design of CMOS Clocking Circuits for Low Phase Noise /

This book contains 11 chapters. The following topics are dealt with: Introduction to phase noise and jitter; CMOS oscillators; Phase noise theory for CMOS oscillators; Introduction to PLL/DLL; PLL loop dynamics and jitter; DLL loop dynamics and jitter; Phase noise suppression techniques 1: subsampli...

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Bibliographic Details
Main Author:	Bae, Woorham
Corporate Author:	Institution of Engineering and Technology
Other Authors:	Jeong, Deog-Kyoon
Format:	eBook
Language:	English
Published:	Stevenage : IET, 2020.
Series:	Materials, Circuits & Devices.
Subjects:	Computer hardware description languages. Electric circuit analysis. Electric interference. Electric noise. Integrated circuits. Integrated circuits > Design and construction. Mathematical models. Noise control. Voltage-controlled oscillators. clocks. CMOS integrated circuits. delay lock loops. digital phase locked loops. hardware description languages. injection locked oscillators. integrated circuit design. integrated circuit modelling. integrated circuit noise. interference suppression. jitter. multiplying circuits. network analysis. phase noise. voltage-controlled oscillators. MOSFET transistor noise System Verilog modeling clock generators voltage-controlled oscillators VCO FoM figure of merits clock multiplying DLL injection locking all-digital PLL subsampling PLL phase noise suppression DLL jitter PLL loop dynamics delay-locked loop phase-locked loop phase noise theory CMOS oscillators low phase noise CMOS clocking circuits analysis CMOS clocking circuits design Electronic books.
Online Access:	Connect to the full text of this electronic book

Description
Summary:	This book contains 11 chapters. The following topics are dealt with: Introduction to phase noise and jitter; CMOS oscillators; Phase noise theory for CMOS oscillators; Introduction to PLL/DLL; PLL loop dynamics and jitter; DLL loop dynamics and jitter; Phase noise suppression techniques 1: subsampling PLL; Phase noise suppression techniques 2: all-digital PLL; Phase noise suppression techniques 3: injection locking; and Phase noise suppression techniques 4: clock multiplying DLL. Appendices on: Figure of merits (FoMs) for evaluating VCOs and PLLs; Survey on state-of-the-art clock generators; System Verilog modeling of CMOS clock generator including jitter; and Noise sources in MOSFET transistor are given.
Physical Description:	1 online resource (255 pages)
ISBN:	9781785618024
DOI:	10.1049/PBCS059E