http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
1 online resource (xvi, 422 pages) : illustrations
Over two volumes this work describes the modelling, design, and implementation of nano-scaled CMOS electronics, and the new generation of post-CMOS devices, at both the device and circuit levels.
Preface; 1. Self-healing analog/RF circuits; 2. On-chip gate delay variability measurement in scaled technology node; 3. Nanoscale FinFET devices for PVT-aware SRAM; 4. Data stability and write ability enhancement techniques for FinFET SRAM circuits; 5. Low-leakage techniques for nanoscale CMOS circuits; 6. Thermal effects in carbon nanotube VLSI interconnects; 7. Lumped electro-thermal modeling and analysis of carbon nanotube interconnects; 8. High-level synthesis of digital integrated circuits in the nanoscale mobile electronics era
9. SPICEless RTL design optimization of nanoelectronic digital integrated circuits10. Green on-chip inductors for three-dimensional integrated circuits: concepts, algorithms and applications; 11. 3D NoC: a promising alternative for tomorrow's nanosystem design; 12. A new paradigm towards performance centric computation beyond CMOS: DNA computing; Index
edited by Saraju P. Mohanty and Ashok Srivastava.
Includes bibliographical references and index.
Metal oxide semiconductors, Complementary
Nano-CMOS and post-CMOS electronics. Circuits and design
London, United Kingdom : The Institution of Engineering and Technology, 2016
Materials, circuits and devices series ; 30