Die-stacking architecture /

Bibliographic Details
Main Authors:	Xie, Yuan, 1973- (Author), Zhao, Jishen (Author)
Format:	eBook
Language:	English
Published:	San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, 2015.
Series:	Synthesis lectures in computer architecture ; # 31.
Subjects:	Computer architecture. Three-dimensional integrated circuits. 3D integrated circuits die-stacking emerging technology heterogeneous integration memory architecture Electronic books.
Online Access:	Connect to the full text of this electronic book

Description
Abstract:	The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.
Physical Description:	1 online resource (xiii, 113 pages) : illustrations. Also available in print.
Format:	Mode of access: World Wide Web. System requirements: Adobe Acrobat Reader.
Bibliography:	Includes bibliographical references (pages 99-111).
ISBN:	9781627057660
ISSN:	1935-3243 ;
DOI:	10.2200/S00644ED1V01Y201505CAC031
Access:	Abstract freely available; full-text restricted to subscribers or individual document purchasers.