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On-chip photonic interconnects : a computer architect's perspective /

Bibliographic Details
Main Authors: Nitta, Christopher J. (Author), Akella, Venkatesh, 1982- (Author), Farrens, Matthew K. (Author)
Format: eBook
Language:English
Published: San Rafael, California (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool, 2014.
Series:Synthesis lectures in computer architecture ; # 27.
Subjects:
Interconnects (Integrated circuit technology)
Nanophotonics.
interconnect
microring
nanophotonics
network topologies
on-chip network
optical interconnects
Electronic books.
Online Access:Connect to the full text of this electronic book
Table of Contents:
  • List of figures
  • List of tables
  • List of acronyms
  • Acknowledgments
  • 1. Introduction
  • 1.1 Organization of the lecture
  • 2. Photonic interconnect basics
  • 2.1 Transmitter
  • 2.1.1 Lasers
  • 2.1.2 Microring resonators
  • 2.1.3 Microrings as modulators
  • 2.2 Transmission medium
  • 2.2.1 Waveguide details
  • 2.2.2 Vias
  • 2.3 Receiver
  • 2.3.1 Photodetector details
  • 3. Link construction
  • 3.1 Photonic link design
  • 3.1.1 Transmitter
  • 3.1.2 Transmission medium
  • 3.1.3 Receiver
  • 3.1.4 Design decisions
  • 3.1.5 Photonic power requirements
  • 3.1.6 Electronic power requirements
  • 3.1.7 Layout/implementation issues
  • 3.1.8 Wide and slow or narrow and fast?
  • 3.1.9 Total power
  • 4. On-chip photonic networks
  • 4.1 Photonic network design challenges
  • 4.1.1 Buffering
  • 4.1.2 Topology
  • 4.1.3 Arbitration and flow control
  • 4.1.4 Electrical/optical codesign
  • 4.1.5 Latency
  • 4.2 Case studies of on-chip photonic networks
  • 4.2.1 Corona
  • 4.2.2 Phastlane
  • 4.2.3 Firefly
  • 4.2.4 Flexishare
  • 4.2.5 DCAF
  • 4.2.6 Hybrid photonic NoC
  • 5. Challenges
  • 5.1 Process variations
  • 5.2 Thermal issues
  • 5.3 Trimming
  • 5.4 Resilient on-chip photonic networks
  • 5.4.1 Photonic link fault models
  • 5.4.2 Link component structure-dependent errors
  • 5.4.3 Unidirectional bit errors
  • 5.4.4 Mean time between failures
  • 6. Other developments
  • 6.1 On-chip network developments
  • 6.1.1 Monolithic CMOS integration
  • 6.1.2 Lasers
  • 6.1.3 Plasmonics
  • 6.2 System-level developments
  • 6.2.1 Off-chip I/O
  • 6.2.2 Memory system
  • 6.2.3 Large-scale routers
  • 7. Summary & conclusion
  • 7.1 Observations and things to remember
  • Bibliography
  • Authors' biographies.