rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Reuse Methodology Manual
    sub title: For System-on-a-Chip Designs
  name:
    name part: Keating, Michael
    name part: 1950 May 2-
    role:
      role term: creator
  name:
    name part: Bricaud, Pierre.
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  genre: Electronic books.
  origin info:
    place:
      place term: mau
    date issued: 1999
    edition: Second edition.
    issuance: monographic
  language:
    language term: eng
  physical description:
    reformatting quality: access
    form: remote
    extent: 1 online resource (xxiii, 286 pages)
  abstract: Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.
  note: by Michael Keating, Pierre Bricaud.
  note: Electronic resource.
  subject:
    topic: Engineering
  subject:
    topic: Computer input-output equipment
  subject:
    topic: Computer-aided design
  subject:
    topic: Computer engineering
  subject:
    topic: Systems engineering
  subject:
    topic: Computers
  classification: TK7888.4
  classification: 621.3815
  identifier: 9781461550372 (electronic bk.)
  identifier: 1461550378 (electronic bk.)
  identifier: 9781461372899
  identifier: 1461372895
  identifier: 1461550378
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: AU@
    record creation date: 121227
    record change date: 20260420202757.3
    record identifier: in00003579944
    language of cataloging:
      language term: eng