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Writing Testbenches: Functional Verification of HDL Models /

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The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. Topics included in the new Second Edition: *Discussions on OpenVera and e;...

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Bibliographic Details
Main Author: Bergeron, Janick
Corporate Author: SpringerLink (Online service)
Format: eBook
Language:English
Published: Boston, MA : Springer US, 2003.
Edition:Second edition.
Subjects:
Engineering.
Computer input-output equipment.
Computer-aided design.
Computer engineering.
Systems engineering.
Electronic books.
Computers.
Online Access:Connect to the full text of this electronic book
Description
Summary:The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. Topics included in the new Second Edition: *Discussions on OpenVera and e; *Approaches for writing constrainable random stimulus generators; *Strategies for making testbenches self-checking; *A clear blueprint of a verification process that aims for first time success; *Recent advances in functional verification such as coverage-driven verification process; *VHDL and Verilog language semantics; *The semantics are presented in new verification-oriented languages; *Techniques for applying stimulus and monitoring the response of a design; *Behavioral modeling using non-synthesizeable constructs and coding style; *Updated for Verilog 2001.
Item Description:Electronic resource.
Physical Description:1 online resource (xxx, 478 pages)
ISBN:9781461503026 (electronic bk.)
1461503027 (electronic bk.)