http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
1 online resource (xxii, 389 pages 132 illustrations)
This monograph surveys architectural mechanisms and implementation techniques for exploiting fine-grained and coarse-grained parallelism within microprocessors. It starts with a review of past techniques, continues with a comprehensive account of state-of-the-art techniques used in microprocessors that covers both the concepts involved and implementations in sample processors, and ends with a thorough review of the research techniques that will lead to future microprocessors.
Basic Pipelining and Simple RISC Processors -- Dataflow Processors -- CISC Processors -- Multiple-Issue Processors -- Future Processors to use Fine-Grain Parallelism -- Future Processors to use Coarse-Grain Parallelism -- Processor-in-Memory, Reconfigurable and Asynchronous Processors -- Acronyms -- Glossary -- References -- Index.
by Jurij Šilc, Borut Robič, Theo Ungerer.