rdf-syntax-grammar
mods:
  schema location: http://www.loc.gov/mods/v3 http://www.loc.gov/standards/mods/v3/mods-3-2.xsd
  title info:
    title: Advanced ASIC Chip Synthesis
    sub title: Using Synopsys® Design CompilerTM and PrimeTime®
  name:
    name part: Bhatnagar, Himanshu.
    role:
      role term: creator
  name:
    name part: SpringerLink (Online service)
  type of resource: text
  genre: Electronic books.
  origin info:
    place:
      place term: mau
    date issued: 1999
    issuance: monographic
  language:
    language term: eng
  physical description:
    reformatting quality: access
    form: remote
    extent: 1 online resource (xxv, 284 pages)
  abstract: Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® describes the advanced concepts and techniques used for ASIC chip synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-arounds described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basics of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solutions. Advanced ASIC Chip Synthesis: Using Synopsys® Design Compiler® and PrimeTime® is intended for anyone who is involved in the ASIC design methodology, starting from RTL synthesis to final tape-out. Target audiences for this book are practicing ASIC design engineers and graduate students undertaking advanced courses in ASIC chip design and DFT techniques. From the Foreword: `This book, written by Himanshu Bhatnagar, provides a comprehensive overview of the ASIC design flow targeted for VDSM technologies using the Synopsis suite of tools. It emphasizes the practical issues faced by the semiconductor design engineer in terms of synthesis and the integration of front-end and back-end tools. Traditional design methodologies are challenged and unique solutions…
  note: by Himanshu Bhathagar.
  note: Electronic resource.
  subject:
    topic: Engineering
  subject:
    topic: Computer-aided design
  subject:
    topic: Computer engineering
  subject:
    topic: Systems engineering
  subject:
    topic: Computer-aided design
  subject:
    topic: Computer engineering
  subject:
    topic: Engineering
  subject:
    topic: Systems engineering
  classification: TK7888.4
  classification: 621.3815
  identifier: 9781441986689 (electronic bk.)
  identifier: 1441986685 (electronic bk.)
  identifier: 9781461346623
  identifier: 1461346622
  identifier: 1441986685
  identifier: http://proxy.library.tamu.edu/login
  record info:
    record content source: AU@
    record creation date: 121227
    record change date: 20260422230200.0
    record identifier: in00003558569
    language of cataloging:
      language term: eng