Formal Equivalence Checking and Design Debugging /

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to...

Full description

Bibliographic Details
Main Author: Huang, Shiyu
Corporate Author: SpringerLink (Online service)
Other Authors: Cheng, Kwang-Ting (Tim)
Format: eBook
Language:English
Published: Boston, MA : Springer US, 1998.
Series:Frontiers in electronic testing ; 12.
Subjects:
Online Access:Connect to the full text of this electronic book
Description
Summary:Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley.
Item Description:Electronic resource.
Physical Description:1 online resource (xviii, 229 pages)
ISBN:9781461556930 (electronic bk.)
1461556937 (electronic bk.)
ISSN:0929-1296 ;